A phase locked loop (PLL) is a circuit that can be used to generate an output clock signal at a selectable output frequency from a reference clock signal at a lower frequency. A classical PLL includes a phase detector that detects a difference in phase between a reference clock signal and a divided down version of the output clock signal. The output clock signal is generated by a voltage controlled oscillator (VCO). The output of the phase detector is used to adjust the output clock frequency by generating an appropriate voltage at the input of the VCO. Many different PLLs are known in the prior art, including analog, digital, and mixed analog and digital PLLs.
In one common PLL design, the VCO exists as a separate integrated circuit and includes its own divider at the output of an oscillator to add greater flexibility in frequency selection. In such a single-chip VCO the value of the divider may be set in response an analog input control voltage for compatibility with various PLL designs. Such a VCO ideally provides perfectly linear frequency selection based on the control voltage. However in modern complementary metal-oxide-semiconductor (CMOS) integrated circuits, power supply voltages have been reduced as speed has increased and power consumption has been reduced. This reduction in power supply voltages has constricted the working headroom of known input buffers that receive the control voltage.
Known input buffers suffer from poor linearity when the input range is a significant fraction of the power supply voltage. One such input buffer is the so-called unity gain follower. The unity-gain follower includes an operational amplifier having a positive input terminal that receives the input voltage, and an output terminal connected to a negative input terminal that provides the output voltage. The unity-gain follower suffers from the drawback that when the input voltage is close the power supply voltage rails, the current source transistors in the amplifier start to come out of saturation, causing the output voltage to no longer be linearly related to the input voltage.
Another input buffer design uses a source follower transistor having a source connected to ground through a resistor divider. The output is taken from an interconnection point of two resistors and the output voltage may be attenuated to allow more headroom. This design has poor noise performance because the system noise will be amplified by the attenuation ratio. The bandwidth requirement is difficult to maintain when low current consumption is required. Furthermore this design cannot recognize signals that are close to ground.
What is needed, then, is an input buffer that is able to operate linearly with a large input voltage range relative to the power supply voltage without introducing other problems, yet can deliver the input signal to further circuitry.